1. Field of the Invention
The present invention relates to an inrush current prevention circuit in a voltage regulator.
2. Description of the Related Art
Now, a conventional voltage regulator is described. FIG. 3 is a circuit diagram illustrating the conventional voltage regulator.
The conventional voltage regulator includes a bias circuit 105, an amplifier 106, N-channel depletion transistors 121, 122, 124, and 125, a PMOS transistor 111, NMOS transistors 123, 126, 127, and 128, resistors 109 and 110, a capacitor 108, inverters 107, 131, and 132, a ground terminal 100, an output terminal 103, a power supply terminal 101, an external terminal 104, and a chip enable terminal 102.
When a control signal input to the chip enable terminal 102 changes from Lo to Hi, the amplifier 106 operates with a current flowing from the bias circuit 105. On the other hand, the NMOS transistor 123 also becomes the ON state because the control signal is Hi. Accordingly, a current I1 flows via the N-channel depletion transistor 122, the NMOS transistor 123, and the external terminal 104, and then the capacitor 108 is charged. When the voltage of the external terminal 104 increases to some extent, the N-channel depletion transistor 125 and the NMOS transistor 126 start to operate and output a reference voltage Vref. Before the rise of the reference voltage Vref, the output of the amplifier 106 is Hi and the PMOS transistor 111 is maintained in the OFF state. Upon the rise of the reference voltage Vref, the output of the amplifier 106 decreases to maintain the PMOS transistor 111 in the ON state, and a voltage Vout of the output terminal 103 starts to rise. When the output voltage Vout increases to some extent, a current I2 starts to flow from the N-channel depletion transistor 124 to the N-channel depletion transistor 125 and the NMOS transistor 126. Then, a voltage VFB divided by the resistors 109 and 110 also increases to maintain the NMOS transistor 127 in the ON state, and the gate voltage of the NMOS transistor 123 decreases to the voltage of the ground terminal 100. Then, the NMOS transistor 123 is turned OFF, and the current I1 flowing to the external terminal 104 abruptly decreases.
On the other hand, the current I2 flowing to the external terminal 104 via the N-channel depletion transistor 124 increases after a while because the current I2 is consumed for charging the capacitor 108. However, the current I2 decreases as the capacitor 108 becomes closer to the fully charged state. When the capacitor 108 is completely charged and the output voltage Vout has completely risen, only a current I3 flows to the N-channel depletion transistor 125 and the NMOS transistor 126. Therefore, even when the capacitor 108 is added, current consumption in the steady state is not increased.
In this way, even when the control signal of the chip enable terminal 102 abruptly rises, the output voltage Vout gradually rises, and, even when a large smoothing capacitor is connected to the output terminal 103, an inrush current flowing to the output terminal 103 can be suppressed (see, for example, Japanese Patent Application Laid-open No. 2011-239130).